1. Field of the Invention
The present invention relates to a method for address arrangement. More particularly, the present invention relates to a method for memory address arrangement.
2. Description of Related Art
As science and technology change quickly, memory develops towards a trend of larger capacity and quicker access speed in correspondence with storage of a large amount of data. The access speed is more required as the memory capacity is larger, and the quicker speed means the higher writing and reading frequency. It is well known that the operation of the memory is mainly writing and reading, so the frequency of writing and reading determines the operating frequency. Therefore, the operating frequency of the memory with large capacity is usually too high to be lowered, such that the minimum value of the operating frequency of the system is limited, which brings higher limitations or requirements to the configuration of other hardware and software of the system. Therefore, it becomes an important technical issue how to lower the access frequency of the memory while keeping or even improving the access speed.
A conventional method is to realize an architecture capable of writing or reading a plurality of units at a time for the memory, in which the memory is divided into several units capable of being respectively reading and writing, and each unit reads and writes an address, thereby achieving a result of reading and writing a plurality of sets of data at a time. For the ease of illustration, the memory is, for example, divided into four units hereinafter. FIG. 1 is a related schematic block diagram of a memory being laterally divided. The memory is laterally divided into four sub blocks, namely sub blocks 101-104, and each sub block includes four longitudinal units represented by letters A-P. Each sub block reads and writes one address at a time, so the memory can read and write four lateral data at a time, for example, ABCD at the first time, EFGH at the second time, IJKL at the third time, and MNOP at the fourth time. In this manner, when it is required to finish the reading and the writing on the data with the same amount at a fixed time, as a plurality of batches of data can be simultaneously read and written at a time, the times of reading and writing can be lowered, and the operating frequency is lowered as well, thereby achieving the objective of improvement. However, in the method of the above example, the memory is laterally divided, so it is only allowed to read and write a plurality of lateral addresses at a time. If it is necessary to read and write a plurality of longitudinal addresses at a time, for example addresses to be read and write are AEIM, BFJN, CGKO, and DHLP, it can not be performed.
For the longitudinal dividing, it is feasible on theory, but practically, burden and limitation on the hardware configuration certainly will be increased, and the related cost is improved, so it is not quite feasible. Further, since it is possible to read and write a plurality of lateral addresses at a time, and the objective of lowering the operating frequency is achieved, is it necessary to further provide a function of reading and writing a plurality of longitudinal addresses at a time? On this point, a liquid crystal display (LCD) is taken as an example, usually a gate driver of the LCD is installed on a longitudinal side of the display panel, and a source driver is installed on a lateral side of the display panel. According to the architecture, the reading of the display memory address data is laterally performed in sequence, so the memory laterally divided can satisfy the requirement. However, as for the hardware configuration requirement, for example a rotatable panel design, the memory is connected to a panel having the source driver disposed laterally, when another function is used, the memory is connected to a panel having the source driver disposed longitudinally, so it is necessary to simultaneously read and write a plurality of batches of lateral data and a plurality of batches of longitudinal data, and thus the memory of the prior art is not available.